This invention relates to drive circuits and more particularly to an address drive circuit for use on electrically programmable, nonvolatile, semiconductor memories.
Electrically Erasable Programmable Read Only Memory Storage (EEPROMS) is accomplished utilizing Metal Nitrite Oxide Semiconductors (MNOS) or "floating gate" transistors for data storage. To address or interrogate the stored data in such memory storage, internal address drive circuits for each word location in storage must be provided. These drive circuits require the capability of switching selectively to one of three supply voltages to provide bias to an array of storage transistors during memory read and write operations and during unselected quiescent conditions. Particularly, during read operations, the selected address drive circuit must output a 5 to 15 volts level to the storage transistors to be read, while the unselected drive circuits provide simultaneously a ground potential. During write operations, the selected address drive circuit must output a full supply level of 20 to 30 volts to the desired storage transistors for periods extending from 1.0 to 100 milliseconds while at the same time the unselected drive circuits provide a ground potential. Finally, during unselected quiescent conditions all drive circuits must output a ground potential.
To achieve this required tristate switching operation, either of two prior art drive circuit designs are commonly used. These designs are known as a static inverter logic gates circuit, which utilizes depletion load transistors, and a "pumped" bootstrap circuit. They have the following common problems:
Both designs have the characteristics of continuously dissipating DC power even when not selected for addressing. In certain applications, this power dissipation becomes a significant portion of the total available memory power since this is a function of the quiescent drive circuit power dissipation multiplied by the number of word locations in memory.
Increased DC power dissipation is experienced in both designs when increasing the speed of the read and write operations. This condition results from the fact that the speed in which a row of storage transistors can be biased for memory read and write operations is a function of the quiescent DC power dissipation of the drive circuits.
Both designs require a relatively large number of transistors/capacitors and control interconnections. As a result, the physical area required by the drive circuits often becomes the limiting factor that determines the practical size of the memory capacity.
It is an object of the present invention to eliminate the virtually steady-state DC power dissipation in the drive circuit.
It is a further object of the invention to increase the speed of memory read and write operations by making the speed of such operations a function of the drive circuit size rather than the DC power dissipation magnitude.
It is still a further object of the present invention to reduce the physical area of the drive circuit while still providing the capability to selectively switch to one of three supply voltages as bias to an array of electrically programmable memory storage transistors, whereby read and write operations can be carried out.